1. Field of the Invention
This invention relates generally to data processing system integrated circuit components and, more particularly, to the redundancy fuse circuits typically used in dynamic random access memory (DRAM) circuits to choose between a logic signal and the complement of the logic signal.
2. Description of the Related Art
An example of a redundancy passgate circuit implemented in complementary metal oxide semiconductor (CMOS) technology, according to the related art, is shown in FIG. 1. The signal Ax.sub.-- is applied to a first conduction terminal of passgate transistor P11. The second conduction terminal of passgate transistor P11 is coupled to the OUTPUT signal terminal. The signal Ax is applied to a first conduction terminal of passgate transistor P12, while a second conduction terminal of passgate P12 is coupled to the OUTPUT signal terminal. The n-channel gate of passgate transistor P11 is coupled to the p-channel gate of passgate P12, to a drain terminal of p-channel transistor T13, and to a drain terminal of n-channel transistor T14 and to a gate terminal of n-channel transistor T15. The n-channel terminal of passgate transistor P12 is coupled to the p-channel gate of passgate P11, to a gate terminal of p-channel transistor T13, to a gate terminal of n-channel transistor T14, to a drain terminal of n-channel transistor T15, to a first terminal of fuse F11, and to a drain terminal of n-channel transistor T12. The SET signal terminal is coupled to a gate terminal of n-channel transistor T12 and to a gate terminal of p-channel transistor T11. A source terminal of n-channel transistor T12, a source terminal of transistor T15, and a source terminal of transistor T14 are coupled to ground terminal. A drain terminal of transistor T11 is coupled to a second terminal of fuse F11, while a source terminal of transistor T11 is coupled to the supply terminal. A source terminal of transistor T13 is coupled to the power supply terminal.
Previous generations of dynamic random access memory units have implemented redundancy fuse circuits using CMOS passgates, such as illustrated in FIG. 1, to chose between a binary logic signal and its complement logic signal. But as the amount of redundancy has been increased on the DRAMs, a need has been felt for passgate circuits operating at higher frequencies which have lowered gate capacitance.